Electronic Design

CMOS Plus On-Chip Electro-Optical Interconnect Zooms Past 2 Tb/s

DARPA, Intel, and Ayar Labs collaborate on developing 100-Tb/s-plus in-package silicon photonic interfaces. Ayar’s TeraPHY chiplet combines silicon photonics and CMOS in a flip-chip SiP. Thermal ...
Semiconductor Engineering

Die-level Thinning and Integrating Route For Singulated MPW Chips Using Both Silicon Sensors and CMOS Devices

“Die-level thinning, handling, and integration of singulated dies from multi-project wafers (MPW) are often used in research, early-stage development, and prototyping of flexible devices. There is a ...